In order to isolate floating gate transistor cells, it is necessary to prevent the formation of channels within bulk areas of the underlying substrate. Accordingly, a large field threshold voltage (V.sub.T) is desirable within the substrate between adjacent floating gates. Such is typically accomplished by optimizing the thickness of intervening field oxide and by providing a raised doping concentration within the substrate beneath the field oxide. If field oxide were made sufficiently thick, it alone could cause a high enough threshold voltage to prevent formation of undesired parasitic channels. Unfortunately, thick field oxide leads to other processing difficulties. To achieve a sufficiently large field threshold voltage with thinner field oxide layers, doping under the field oxide is typically increased. The resultant implant is typically referred to as a "channel stop".
The prior art provides such implants either before or after field oxide formation. For example with respect to pre-field oxide formation, a conductivity enhancing impurity of an appropriate type would be implanted into the silicon substrate in regions where field oxide will subsequently be formed. During field oxidation, the implant experiences both segregation and oxidation-enhanced diffusion. Thus, relatively high boron doses are needed in order for acceptable field threshold voltages to be achieved. This also implies that the peak of the dopant implant must be deep enough so that it is not absorbed by the growing field-oxide interface. However if the channel stop doping is too heavy, it will cause high source/drain-to-substrate capacitances, and will reduce source/drain-to-substrate pn junction breakdown voltages.
With respect to post-field oxide formation implantation, ion implantation of the desired dopant is conducted through the field oxide at a selected energy and dose to position a channel stop implant immediately therebeneath.
An example prior art construction and problems associated therewith is described with reference to FIG. 1. There illustrated is a semiconductor wafer fragment 10 comprised of a bulk substrate or well region 12, gate oxide region 14, and field oxide region 16. Outline area 18 depicts a region which will be doped subsequently for formation of a source or drain of a floating gate programmable read only memory cell transistor. Region 20 depicts the formed and desired outline of a channel stop implant region effective for isolating region 18 from other source/drain areas of other transistors formed within bulk substrate 12.
Regardless of pre or post field oxide formation implanting, lateral diffusion of the implant material undesirably causes encroachment into the adjacent active area. Inherent subsequent heating of the substrate, the result of subsequent depositions and other processing, can typically cause implant region 20 to expand for example to outline 22 depicted in FIG. 1. This diffusion is undesirably magnified in the fabrication of floating gate transistor cells which utilize ONO as one of the dielectric layers. The steps utilized to form ONO dielectric layers occur at high temperatures which promotes redistribution of the implant.
Accordingly, such redistribution raises the dopant surface concentration near the edge of the field oxide, causing the threshold voltage to undesirably increase in that region of the active device. As a result, the edge of the device will not conduct as much current as the interior portion, and the transistor will behave as if it were a narrower device. The effect is also undesirably enhanced as the dose of the channel stop implant is increased.
It would be desirable to overcome some of these drawbacks in methods specific to forming floating gate programmable read only memory cell transistors.